The present invention relates to a memory control circuit and a memory control method for controlling access to memory, and in particular, to access control of virtual channel memory such as virtual channel SDRAM having a plurality of virtual channels.
The demand for speeding up of synchronous memory is growing more and more these years. A technique effective for the speeding up is virtual channel synchronous DRAM (hereafter referred to as xe2x80x9cVCSDRAMxe2x80x9d).
The VCSDRAM has several features (input/output circuitry synchronized by an external clock signal, access by use of commands, access by means of burst transfer, etc.) which are common to synchronous DRAM. However, the VCSDRAM is provided with a plurality of high-speed registers called xe2x80x9cvirtual channelsxe2x80x9d (hereafter, also referred to as xe2x80x9cchannelsxe2x80x9d) in addition to ordinary SDRAM memory cells. Each of the virtual channels can be controlled separately and independently.
In VCSDRAM, read/write operation from outside is conducted directly to each channel as foreground processing, differently from the case of ordinary SDRAM. Meanwhile, intra-memory processes of the VCSDRAM such as data transfer between a memory cell and a channel, precharge of memory cells, refresh, etc. are executed as background processing which is independent of the foreground processing. Therefore, the foreground processing and the background processing can be executed concurrently in VCSDRAM.
In the following, the basic operation of VCSDRAM will be explained referring to Figures. FIG. 1 is a schematic block diagram for explaining the operation of VCSDRAM.
When data is read out from VCSDRAM 150 (read operation), data readout is executed not from memory cells of the memory cell array 151 but valid data is read out from a channel 152, differently from the case of ordinary SDRAM (hereafter, the read operation in the VCSDRAM 150 will be referred to as xe2x80x9cchannel read operationxe2x80x9d). In the same way, when data is written into the VCSDRAM 150 (write operation), data writing is not executed directly to memory cells but valid data is written to a channel 152 (hereafter, the write operation in the VCSDRAM 150 will be referred to as xe2x80x9cchannel write operationxe2x80x9d). Hereafter, the operation of the VCSDRAM 150 for copying part of valid data from memory cells to a channel 152 will be referred to as xe2x80x9cprefetch operationxe2x80x9d. On the other hand, the operation of the VCSDRAM 150 for copying valid data from a channel 152 to memory cells and overwriting old data of the memory cells with the data of the channel 152 will be referred to as xe2x80x9crestore operationxe2x80x9d.
For the completion of the write operation of the VCSDRAM 150 (that is, for the update of valid data in the memory cells), the restore operation has to be executed after the channel write operation.
Data transfer between a channel 152 and memory cells is generally executed in units of data transfer minimum units which are called xe2x80x9csegmentsxe2x80x9d. The size of each segment is generally set to 1/4 of a row address size (the size of each row in the address space).
In the read operation, when valid data exists in a channel 152 (hereafter called xe2x80x9cchannel hitxe2x80x9d), the channel read operation is executed by a memory controller. Such operation will hereafter be called xe2x80x9chit A readxe2x80x9d.
When valid data does not exist in a channel 152 (hereafter called xe2x80x9cchannel missxe2x80x9d) and the row address of the valid data in the memory cells has been in xe2x80x9cActive Standbyxe2x80x9d status, the valid data is first transferred to the channel 152 by the prefetch operation and thereafter the channel read operation is executed. Such operation will hereafter be referred to as xe2x80x9chit B readxe2x80x9d.
When the xe2x80x9cchannel missxe2x80x9d occurred and a row address that is different from a row address where the valid data exists has been in the Active Standby status (hereafter called xe2x80x9crow missxe2x80x9d), the status of the row address where the valid data exists is turned to the Active Standby status, the valid data is transferred to the channel 152 by the prefetch operation, and thereafter the channel read operation is executed. Such operation will hereafter be referred to as xe2x80x9cmiss readxe2x80x9d.
In the case of xe2x80x9cmiss readxe2x80x9d, if another background operation (operation which is executed as background processing) is during execution, the execution of the prefetch operation and the channel read operation have to be suspended until the background operation is completed. Therefore, such a wait for the completion of background operation in the case of xe2x80x9cmiss readxe2x80x9d etc. causes the delay of newly occurring access.
In the following, the operation of a conventional memory controller in the case of xe2x80x9cchannel missxe2x80x9d will be explained referring to FIGS. 2 and 3. FIG. 2 is a timing chart showing the operation of the conventional memory controller when access requests occurred. FIG. 3 is a schematic block diagram showing an example of the composition of a VCSDRAM module which is controlled by the conventional memory controller.
The timing chart of FIG. 2 shows a case where three memory access requests are supplied from memory masters 130. The three memory access requests will be assumed to be read requests, and the three read requests will be referred to as xe2x80x9cread request #1xe2x80x9d, xe2x80x9cread request #2xe2x80x9d and xe2x80x9cread request #3xe2x80x9d in order of occurrence. A memory row address and a segment that occur in the read request #1 will be described as xe2x80x9cRow1xe2x80x9d and xe2x80x9cSeg1xe2x80x9d. In the same way, memory row addresses and segments that occur in the read requests #2 and #3 will be described as xe2x80x9cRow2xe2x80x9d, xe2x80x9cSeg2xe2x80x9d, xe2x80x9cRow3xe2x80x9d and xe2x80x9cSeg3xe2x80x9d, respectively. Further, column addresses that occur in the read requests #1, #2 and #3 will be described as xe2x80x9cCol1xe2x80x9d, xe2x80x9cCol2xe2x80x9d and xe2x80x9cCol3xe2x80x9d, respectively.
It is assumed that the read requests #1 and #2 designate the same memory row address, the same segment and different column addresses. The read request #3 is assumed to designate access to a row address that is different from that of the read requests #1 and #2. Further, it is assumed that each memory cell of the VCSDRAM module is in xe2x80x9cIDLE statusxe2x80x9d (that is, neither bank nor channel is active).
First, for the read request #1, the conventional memory controller (which knows that the current status of the VCSDRAM module is the IDLE status) supplies the memory row address xe2x80x9cRow1xe2x80x9d to the memory (VCSDRAM module) by use of an ACT (bank active) command, turns a bank A of the memory to the Active Standby status, gives xe2x80x9cSeg1xe2x80x9d to the memory by use of a PFC (prefetch) command, and thereby transfers valid data to a channel #1. Thereafter, the conventional memory controller supplies the column address xe2x80x9cCol1xe2x80x9d to the memory by use of a READ (channel read) command and thereby data #1 (da00xcx9cda03) are read out from the channel #1, thereby the memory read operation for the read request #1 is completed.
Subsequently, when the read request #2 is supplied, the conventional memory controller judges that it is xe2x80x9cchannel hitxe2x80x9d since the read requests #1 and #2 designate the same memory row address, the same segment and different column addresses. Therefore, the conventional memory controller issues a READ command to the channel #1, supplies the column address xe2x80x9cCol2xe2x80x9d, and thereby reads data #2 (db00xcx9cdb03) from the channel #1 (that is, executes the aforementioned xe2x80x9chit A readxe2x80x9d), thereby the memory read operation for the read request #2 is completed.
Finally, in the case of the read request #3, valid data does not exist in a channel, and a row address that is in the Active Standby status is different from a row address where valid data for the read request #3 exists. Therefore, the case is xe2x80x9crow missxe2x80x9d. The conventional memory controller first turns the bank A (which is currently in the Active Standby status) into IDLE status by use of a PRE (precharge) command. Subsequently, the conventional memory controller supplies the memory row address xe2x80x9cRow3xe2x80x9d to the memory by use of an ACT command, turns a bank B of the memory to the Active Standby status, gives xe2x80x9cSeg3xe2x80x9d to the memory by use of a PFC command, and thereby transfers valid data to a channel #2. Thereafter, the conventional memory controller supplies the column address xe2x80x9cCol3xe2x80x9d to the memory by issuing a READ command and thereby reads data #3 (da10xcx9cda13) from the channel #2, thereby the memory read operation for the read request #3 is completed.
As described above, the conventional memory controller conducts the accesses to the virtual channel memory in order of access requests (that is, in order of arrival of the access requests). Therefore, there are cases where the execution of memory access takes long time (in the case of xe2x80x9cchannel missxe2x80x9d etc.) due to the wait which is caused by background operation (prefetch etc.) as seen in FIG. 2.
It is therefore the primary object of the present invention to provide a memory control circuit and a memory control method for executing memory control of virtual channel memory such as VCSDRAM, by which command sequence (the order of execution of commands) is optimized for preventing the deterioration of data transfer rate and thereby efficient use of the virtual channel memory is realized.
In accordance with a first aspect of the present invention, there is provided a memory control circuit for executing access control of a virtual channel memory module, comprising an access request reception means (10), an access request storage means (20), a status comparison means (30), a preceding command control means (50), a state control means (40), and a command/address generation means (60, 70). The access request reception means receives access requests which are supplied from memory masters (3). The access request storage means stores the access requests received by the access request reception means (10) and generates a foreground command request signal for each access request. The status comparison means (30) compares each access request with the current status of the virtual channel memory module. The preceding command control means (50) generates a background command request signal for each access request if necessary for the execution of the access request based on the comparison executed by the status comparison means (30). The state control means (40) receives the foreground command request signals and the background command request signals which are supplied from the access request storage means (20) and the preceding command control means (50), assigns priorities to commands according to a predetermined standard by reference to the command request signals, and thereby generates requests for controlling the issue of the commands to the virtual channel memory module. The command/address generation means (60, 70) generates the commands and addresses for the access control of the virtual channel memory module according to the requests which are supplied from the state control means (40).
In accordance with a second aspect of the present invention, in the first aspect, the access request storage means (20) includes an access request signal storage means (21), a foreground command selection means (22), and a foreground command request signal generation means (23). The access request signal storage means (21) stores access request signals which are supplied from the access request reception means (10). The foreground command selection means (22) withdraws each access request signal from the access request signal storage means (21) and selects an appropriate foreground command for each access request signal. The foreground command request signal generation means (23) generates the foreground command request signal for each access request and sends the foreground command request signal to the state control means (40) so that the foreground command selected by the foreground command selection means (22) will be issued.
In accordance with a third aspect of the present invention, in the first aspect, the status comparison means (30) includes an access request signal storage means (31), a memory status storage means (33), a memory status update means (32), a comparison means (34), a background operation judgment means (35), a background operation request signal generation means (36), and a channel validity judgment means (37). The access request signal storage means (31) stores access request signals which are supplied from the access request reception means (10). The memory status storage means (33) stores memory status information concerning the current status of the virtual channel memory module. The memory status update means (32) receives a background command occurrence signal which is supplied from the preceding command control means (50) and thereby updates the memory status information stored in the memory status storage means (33). The comparison means (34) withdraws each access request signal from the access request signal storage means (31) and compares the access request signal with the memory status information stored in the memory status storage means (33). The background operation judgment means (35) judges whether or not background operation is necessary for the execution of the access request and determines the contents of the background operation based on the result of the comparison executed by the comparison means (34). The background operation request signal generation means (36) generates a background operation request signal based on the contents of the background operation determined by the background operation judgment means (35) and sends the background operation request signal to the preceding command control means (50) if the background operation judgment means (35) judged that the background operation is necessary. The channel validity judgment means (37) judges whether a channel designated by the access request is valid or not based on the result of the comparison executed by the comparison means (34) and sends the result of the judgment to the access request storage means (20).
In accordance with a fourth aspect of the present invention, in the first aspect, the state control section (40) includes a foreground command request signal storage means (41), a background command request signal storage means (42), a command request signal ordering means (43), a command request signal supply means (44), and a memory bus monitoring means (45). The foreground command request signal storage means (41) stores the foreground command request signals which are supplied from the access request storage means (20). The background command request signal storage means (42) stores the background command request signals which are supplied from the preceding command control means (50). The command request signal ordering means (43) withdraws the foreground command request signals and the background command request signals from the foreground command request signal storage means (41) and the background command request signal storage means (42), assigns priorities to the command request signals according to a predetermined standard by associating the command request signals with corresponding access requests, and arranges and orders the command request signals in order of the priority. The command request signal supply means (44) supplies the ordered command request signals one by one to the command/address generation means (60, 70). The memory bus monitoring means (45) monitors the status of a memory bus according to signals supplied from the command/address generation means (60, 70) and informs the command request signal ordering means (43) about the memory bus status.
In accordance with a fifth aspect of the present invention, in the fourth aspect, in the ordering by the command request signal ordering means (43): the foreground command request signals and the background command request signals are arranged in order of corresponding access requests giving higher priority to a background command request signal corresponding to an access request than a foreground command request signal corresponding to the same access request, and the timing of the background operation to be executed by the background command is advanced to a point where the background operation barely avoids alteration of channel from the channel used by a foreground operation for a preceding access request, satisfying the conditions that: (A) an operation for a background command that is hitting a bank of the memory cell array should be executed with high priority in the execution of the operation; and (B) if the memory bus can not accept a background command but a foreground operation for a preceding access request is executable, the foreground operation should be executed prior to the background command.
In accordance with a sixth aspect of the present invention, in the first aspect, the memory control circuit is employed for the access control of a VCSDRAM (Virtual Channel SDRAM) module.
In accordance with a seventh aspect of the present invention, there is provided a memory control method for the access control of a virtual channel memory module. The memory control method comprises an access request storage step, a background processing necessity judgment step, a background command request signal generation step, a foreground command request signal generation step, a command request signal ordering step, a background operation advancing step, and a memory control step. In the access request storage step, each access request is stored in an access request storage means (20) when the access request is supplied from a memory master (3). In the background processing necessity judgment step, each access request is withdrawn one by one from the access request storage means (20) and it is judged whether or not background processing is necessary for the execution of the access request. In the background command request signal generation step, a background command request signal is generated for the access request if the background processing for the execution of the access request has been judged to be necessary in the background processing necessity judgment step. In the foreground command request signal generation step, a foreground command request signal is generated for the access request regardless of whether or not the background processing is necessary. In the command request signal ordering step, the background command request signals and the foreground command request signals generated for the access requests are arranged and ordered in order of the access requests so that a background command request signal for an access request will be given higher priority than a foreground command request signal for the same access request. In the background operation advancing step, the timing of a background operation to be executed by the background command is advanced to a point where the background operation barely avoids alteration of channel from the channel used by a foreground operation for a preceding access request. In the memory control step, command requests are supplied one by one to a command generation means (60) and an address generation means (70) and thereby access control of the virtual channel memory module is executed.
In accordance with an eighth aspect of the present invention, in the seventh aspect, the memory control method is employed for the access control of a VCSDRAM (Virtual Channel SDRAM) module.
In accordance with a ninth aspect of the present invention, there is provided a memory control method for the access control of a virtual channel memory module. The memory control method comprises an access request reception step, an access request storage step, a status comparison step, a preceding command control step, a state control step, and a command/address generation step. In the access request reception step, access requests which are supplied from memory masters (3) are received. In the access request storage step, the access requests received in the access request reception step are stored and a foreground command request signal is generated for each access request. In the status comparison step, each access request is compared with the current status of the virtual channel memory module. In the preceding command control step, a background command request signal is generated for each access request if necessary for the execution of the access request based on the comparison executed in the status comparison step. In the state control step, the foreground command request signals and the background command request signals generated in the access request storage step and the preceding command control step are stored, priorities are assigned to commands according to a predetermined standard by reference to the command request signals, and thereby requests for controlling the issue of the commands to the virtual channel memory module are generated. In the command/address generation step, the commands and addresses for the access control of the virtual channel memory module are generated according to the requests which are generated in the state control step.
In accordance with a tenth aspect of the present invention, in the ninth aspect, the access request storage step includes an access request signal storage step, a foreground command selection step, and a foreground command request signal generation step. In the access request signal storage step, access request signals which are generated in the access request reception step are stored in an access request signal storage means (21). In the foreground command selection step, each access request signal is withdrawn from the access request signal storage means (21) and an appropriate foreground command is selected for each access request signal. In the foreground command request signal generation step, the foreground command request signal is generated for each access request so as to be used in the state control step so that the foreground command selected in the foreground command selection step will be issued.
In accordance with an eleventh aspect of the present invention, in the ninth aspect, the status comparison step includes an access request signal storage step, a memory status storage step, a memory status update step, a comparison step, a background operation judgment step, a background operation request signal generation step, and a channel validity judgment step. In the access request signal storage step, access request signals which are generated in the access request reception step are stored in an access request signal storage means (31). In the memory status storage step, memory status information concerning the current status of the virtual channel memory module is stored in a memory status storage means (33). In the memory status update step, the memory status information stored in the memory status storage means (33) is updated according to a background command occurrence signal which is generated in the preceding command control step. In the comparison step, each access request signal is withdrawn from the access request signal storage means (31) and the access request signal is compared with the memory status information stored in the memory status storage means (33). In the background operation judgment step, it is judged whether or not background operation is necessary for the execution of the access request and the contents of the background operation are determined based on the result of the comparison executed in the comparison step. In the background operation request signal generation step, a background operation request signal is generated based on the contents of the background operation determined in the background operation judgment step so as to be used in the preceding command control step if the background operation has been judged to be necessary in the background operation judgment step. In the channel validity judgment step, it is judged whether a channel designated by the access request is valid or not based on the result of the comparison executed in the comparison step so that the result of the judgment will be used in the access request storage step.
In accordance with a twelfth aspect of the present invention, in the ninth aspect, the state control step includes a foreground command request signal storage step, a background command request signal storage step, a command request signal ordering step, a command request signal supply step, and a memory bus monitoring step. In the foreground command request signal storage step, the foreground command request signals generated in the access request storage step are stored in a foreground command request signal storage means (41). In the background command request signal storage step, the background command request signals generated in the preceding command control step are stored in a background command request signal storage means (42). In the command request signal ordering step, the foreground command request signals and the background command request signals are withdrawn from the foreground command request signal storage means (41) and the background command request signal storage means (42), priorities are assigned to the command request signals according to a predetermined standard by associating the command request signals with corresponding access requests, and the command request signals are arranged and ordered in order of the priority. In the command request signal supply step, the ordered command request signals are given one by one to the command/address generation step. In the memory bus monitoring step, the status of a memory bus is monitored according to signals generated in the command/address generation step so that the memory bus status will be used in the command request signal ordering step.
In accordance with a thirteenth aspect of the present invention, in the twelfth aspect, in the ordering which is executed in the command request signal ordering step: the foreground command request signals and the background command request signals are arranged in order of corresponding access requests giving higher priority to a background command request signal corresponding to an access request than a foreground command request signal corresponding to the same access request, and the timing of the background operation to be executed by the background command is advanced to a point where the background operation barely avoids alteration of channel from the channel used by a foreground operation for a preceding access request, satisfying the conditions that: (A) an operation for a background command that is hitting a bank of the memory cell array should be executed with high priority in the execution of the operation; and (B) if the memory bus can not accept a background command but a foreground operation for a preceding access request is executable, the foreground operation should be executed prior to the background command.
In accordance with a fourteenth aspect of the present invention, in the ninth aspect, the memory control method is employed for the access control of a VCSDRAM (Virtual Channel SDRAM) module.
In accordance with fifteenth through twenty-second aspects of the present invention, there are provided machine-readable record mediums storing programs for instructing an MPU (MicroProcessor Unit) etc. to execute the memory control methods of the seventh through fourteenth aspects of the present invention.